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臺積電2022屆招聘簡章
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招聘會詳情

臺積電(南京)有限公司是臺積電在南京全資設立的子公司,公司投資30億美元在江北新區興建12寸晶圓廠暨設計服務中心,2016年7月7日舉行新廠奠基大典,創辦人張忠謀親自主持開工,強調兩岸集成電路(ic)產業應該共同發展,推動兩岸經濟互利合作。創辦人張忠謀表示,臺積電南京將發揮供應鏈與人才優勢,會是大陸第一座能夠在地量產16奈米製程的12寸晶圓廠。 近年來,大陸半導體市場成長快速,臺積電在大陸的業務也強勁成長。為了就近服務客戶,我們在南京成立設計服務中心,將臺積電的“開放創新平臺”生態系統導入大陸,協助大陸的ic設計公司,一起發展半導體產業、共同成長。

招聘詳情

臺積電2022屆招聘簡章

工作地點:南京

臺積電介紹

臺積公司成立于1987年,全球專業集成電路制造領域龍頭,全球利潤率排名第一。擁有281種制程技術,為510個客戶生產1萬1617種不同產品,擁有52%市場占有率。世界首家提供現今最先進的5奈米制程技術,全世界最大的專業集成電路制造服務公司。

臺積電(南京)

臺積電(南京)有限公司成立于2016年,位于南京浦口經濟開發區,是臺積電獨資設立的子公司,生產12英寸晶圓,同時成立南京設計服務中心,以最先進的芯片設計技術服務客戶。

臺積電南京創造了臺積很多新的里程碑,包含建廠速度最快、量產最快、獲利最快。

校園招聘流程安排:

招募流程:網申→筆試→(線上+線下)面試→錄用通知→加入臺積

網申時間:2022/2/17~4/30

投遞鏈接:http://2022.yingjiesheng.com/tsmc/jobs.html

職位列表 (所有崗位應屆/往屆生均可投遞)

職位專業要求學歷
設備工程師理工科專業本科/碩士
制程工程師材料、電子、化學、物理、光學等碩士
制程整合工程師微電子碩士
ic設計工程師微電子、電子科學與技術、計算機科學等碩士
智能制造工程師工業工程、制造、工業管理、信息系統、機械與自動化工程碩士

晶彩臺積:對臺積人而言,生活的豐富和專業的成就同等重要;從食衣住行的滿足到精神層面的提升,臺積人在臺積獲得充分的照顧。

這里擁有:

完善的保險制度:我們除依法為員工繳納五險一金外,更為員工規劃了團體商業保險福利,以增加員工整體之保障。

彈性的假期制度:臺積電提供優于勞動法的特別休假制度,員工到職滿三個月即可享有,加上彈性的休假制度,方便員工于一年中排定假期。我們并依法給予各種假別,當同仁有請假需求時,能夠更無后顧之憂。

貼心的工作環境:我們體貼并照顧同仁的工作及生活所需,在醫、食、住、行、樂領域提供全方位的服務與設施,使同仁能輕松兼顧工作與生活。

這里更有:

完善的餐飲及健身設施,貼心關懷的駐廠門診、按摩及全天候的護理協助,免費年度健康檢查服務,溫馨舒適、設施完善的宿舍,多條線路的交通班車貫通供員工免費搭乘,環保典范的工作環境是臺積人享有的安心福利。

歡迎志同道合的您加入臺積電,一同釋放全世界的創新!

申請職位

1、設備工程師

【職責范圍】

1.;負責薄膜、黃光、蝕刻、離子擴散、機械研磨等設備機臺的維護及效能精進。

2.;處理高科技設備故障。

3.;提高設備效率。

4.;計劃和執行分析或缺陷檢測項目。

5.;與跨職能工程師或供應商溝通。

【職位要求】

1.;本科/碩士學歷。電子、電氣、機械及自動化相關專業。

2.;無需經驗(有設備維護或改進經驗者優先)。

3.;具備基本的機械相關知識。有半導體工藝知識者優先。

4.;良好的解決問題能力,溝通能力,團隊精神,積極的學習態度,英語能力強。

2、制程工程師

【職責范圍】

1.;在線問題處理:解決在線制程問題,確保流程的順暢,協助新制程導入與技術轉移,解決工藝異常及減少工藝缺陷,產品良率。

2.;計劃并執行改進制程良率與降低制造成本的項目,提升及改善工藝能力。

3.;與器件,整合,良率提升,制程整合,制造部等多部門跨部門合作。

【職位要求】

1.;良好的解決問題能力,溝通能力,團隊精神,積極的學習態度,英語能力強。

2.;具有良好的開放式溝通能力,能夠在跨職能團隊中工作,包括內部和外部合作伙伴。

3.;英語流利。

4.;較強的統計過程控制(spc)和/或實驗設計(doe)原理知識。

5.;需要基于基礎而非經驗模型的強大的技術問題解決和分析能力。

6.;動手參與和強烈的主人翁精神。

7.;可以適應fab內的工作環境,接受小夜班。

3、制程整合工程師

【職責范圍】

1.;確保芯片的質量、持續提升良率,提供給客戶具有競爭力且高質量的芯片,讓電子產品不但先進且效能穩定;

2.;制程整合工程師為半導體制造中的重要協調者,需要與客戶溝通了解客制化的芯片應用需求,再將訊息帶回廠內,與各工程單位合作,提升產品的良率與質量;

3.;良率精進工程師監控芯片的良率與缺陷,使用量測機臺監測芯片的缺陷,找出可能的問題,再與制程解決問題。

【職位要求】

1.;微電子等相關領域知識的碩士優秀應征者;

2.;有較好的半導體組件物理與電性知識/英文與溝通能力/領導與問題解決能力;

3.;可將程序語言作為良率改善工具。

4、ic設計工程師 (具體設計崗位如下)

4.1sram design engineer(靜態隨機存儲器設計工程師)

【職責范圍】

1.;develop sram/rom compilers and customized macros.

2.;develop sram/rom characterization flow and deliver design kits.

3.;develop memory compiler tiling code.

【職位要求】

1.;candidate must have a ms degree or above in electrical or computer engineering

2.;knowledge on transistor level circuit design and layout design.

3.;experience in spice simulation or fast spice simulation.

4.;familiarity with verilog and synopsys .lib.

5.;ability in scripting language, such as perl/python/shell/tcl

4.2 digital circuit design engineer(數字電路設計工程師)

【職責范圍】

1.;develop advanced standard cell and gpio libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)

2.;take challenging tasks from circuit design to soc design to achieve world-class ppa performance (high-performance, low-power, and area-effective)

【職位要求】

1.;good knowledge of circuits design. experience in digital circuit or analog design is preferred.

2.;experience in cadence/synopsys/mentor eda tools and linux/unix environment is preferred

3.;cad and script capability such as python/perl/shell is preferred.

4.;solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced finfet nodes is a plus.

5.;experience in reliability (em, high-temperature aging effects, etc.) is a plus

6.;self-motivated and hard work.

4.3ic frontend design engineer(芯片前端設計工程師)

【職責范圍】

1.;rtl synthesis, sdc/upf verification, low power design implementation for advanced technology chips.

2.;design flow/methodology development and innovation for front-end design challenges.

3.;be responsible for rtl verification, synthesis, low power design, and sta/timing closure works for customer’s projects and internal system test chips.

【職位要求】

1.;ms or above in ee, cs related fields. experience in digital ic design flow (from synthesis, dft, mbist, formality, sta), rtl design, rtl verification is plus.

2.;new graduate or 3+ years working experience.

3.;familiar with ee cad tool such as design compiler, dft complier, mbist, n-lint, verdi, verilog tools/flows.

4.;familiar with tcl/perl/python program.

4.4ic physical design engineer(芯片物理設計工程師)

【職責范圍】

1.;physical implementation of advanced technology chips.

design methodology development and innovation for advanced technology challenges.

2.;be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.

3.;be responsible for advanced node ppa benchmark, and solution development.

4.;eda tool new features enablement.

5.;customer onsite/offsite supports will be required on demand.

【職位要求】

1.;ms or above in ee, cs related fields. experience in apr, physical verification, chip implementation, or cad development is plus.

2.;new graduate or 3+ years working experience in chip physical implementation.

familiar with synopsys/cadence apr tools/flows.

3.;familiar with tcl/perl/python programming.

4.;experience with tsmc advanced technology is plus.

5.;proven record in production tape-outs is plus.

4.5ic cad and methodology engineer(芯片計算機輔助設計暨設計方法論工程師)

【職責范圍】

1.;develop chip implementation infrastructure, include but not limited to general design flow automation, design collateral/environment/data management, computing resource allocation/analysis/monitoring, and design diagnosis solutions development.

2.;develop chip implementation methodology algorithms to improve productivity and design ppa by machine learning and/or expert system programming.

3.;develop chip implementation environment regression automation and code review system to improve source code quality and readability.

【職位要求】

1.;ms degree or above in ee, cs related fields.

2.;proactive, self-motivated, and willing to take challenges

3.;familiar with python3 or c/c++ programming languages

4.;familiar with linux environment and operations

recommended requirements (plus):

1.;familiar withsoftware engineering or electronic design automation algorithms

2.;familiar with perl, tcl/tk programming languages

3.;familiar with sql, php, javascript, html/ccs webpage development

4.;experienced in vlsi design flow and apr tool usage

5.;familiar with data visualization, data mining or machine learning algorithms

6.;paper publication records

4.6ic signoff engineer(芯片簽核工程師)

【職責范圍】

1.;responsible for checking the advanced chip function before fabrication. given the verification, the chip can exhibit expecting high performance after fabrication.

2.;reliable flow setting, identify violation root cause, and provide the fixing strategy to achieve high quality chips.

3.;professional at one domain of blow knowledge at least. signoff team not only executes the advanced signoff skill, but also push the boundary of flow to reach higher quality and productivity.

a.;sta (static timing analysis): using commercial timing signoff eda tool combining advanced on-chip timing analysis method (ocv) to achieve timing closure before tape-out.

b.;ir analysis: define the reasonable ir drop spec, and explore the opportunity to realize the function with sufficient voltage support and reasonable power consumption.

c.;pv (physical verification): verify and achieve the chip without drc (design rule check) and lvs (layout versus schematic). with the verification, the following fabrication can minimize the defect and reach high yield performance.

【職位要求】

1.;ms degree or above in ee, cs, physics or related domains. experience in digital ic design flow, especially signoff, is a plus

2.;innovative, persistence and flexible personality.

3.;for frequent cross team cooperation and customer support, excellent communication/presentation skill

recommended requirements (plus):

1.;excellent english skill, cet6

2.;software skill, ex: tcl, python

4.7 layout engineer(ip版圖設計工程師)

【職責范圍】

1.;full layout design for standard cell/io/sram ips in advanced process nodes

2.;work on the physical verification (drc/lvs/antenna ...)

3.;work on test chip layout design and verification

4.;close cooperation with designers on ppa optimization

【職位要求】

1.;at least bs degree of microelectronics or physics.

2.;excellent graduate or at least 1 years' related working experience

3.;familiar with layout design and verification tools (virtuoso, laker, calibre)

4.;familiar with design rule and layout effect in advanced process.

5.;excellent skills of communication and teamwork are also expected.

6.;programming experience (perl/tcl skill) will be a plus.

7.;experience in advanced process (n16 and beyond) will be a plus.

4.8 drc/lvs development engineer(drc/lvs開發工程師)

【職責范圍】

1.;work closely with process rd team to develop drc/lvs for design readiness.

2.;provide customer support to world-wide leading design house.

3.;initial more innovation to continue optimize development efficiency.

4.;work closely with various departments (physical design/integration/device rd/product/esd) on their design requirements.

5.;work closely with eda partner for tool qualification and methodology enhance.

【職位要求】

1.;good knowledge of semiconductor feol/beol process and chip design concepts. solid understanding of device physics, layout design is a plus.

2.;knowledge of eda partner (mentor, synopsys, cadence, etc.) tools suite is a plus. especially laker /virtuoso /calibre.

3.;scripting and programming experience using several of the following: perl, python, c, c++, tcl, skill.

4.;ability to work across teams to drive a solution, problem solver and self-motivated.

5.;the ideal candidate will have experience in drc/lvs development.

6.;ms or above in ee, cs related fields.

5、智能制造工程師

【職責范圍】

1.;創造晶圓產出最大化,滿足客戶交期,為公司帶來營收。

2.;掌握生產流程,藉由良好且精準派工提升機臺生產效率,帶領技術員團隊確保制造流程順暢運行并達成每日的產能目標。

【職位要求】

1.;工業工程、制造工程、資訊工程、商管統計知識

2.;運用大數據分析、機器學習優化生產排程

3.;領導力與溝通技巧,抗壓能力需具備om,ie或it相關領域。

投遞流程:

注冊今日招聘(https://www.jrzp.com/xiaozhaoView/1829790.shtml),完善個人簡歷或上傳pdf版簡歷>>選中職位投遞>>確認職位或崗位名稱>>完成投遞,并注意盡量不要多崗投遞。

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